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application note AN4138 design considerations for battery charger using green mode fairchild power switch (fps tm ) www.fairchildsemi.com ?2003 fairchild semiconductor corporation abstract this application note presents practical design consider- ations for battery chargers employing green mode fps (fairchild power switch). it includes designing the transformer and output filter, selecting the components and implementing constant current / constant voltage control. the step-by-step design procedure described in this paper will help engineers design battery chargers more easily. in order to make the design process more efficient, a software design tool, fps design assistant that contains all the equations described in this paper is also provided. the design procedure is verified through an experimental prototype converter. rev. 1.0.0 1. introduction as penetration rates of portable electronics devices such as cellular phones, digital cameras or pdas have increased significantly, the demands for low cost battery chargers are rising these days. fairchild power switch (fps) reduces total component count, design size, weight and, at the same time increases efficiency, productivity, and system reliability when compared to a discrete mosfet and controller or rcc switching converter solution. table 1 shows the fps lineup for a battery charger application. figure 1 shows the schematic of the basic battery charger using fps, which also serves as the reference circuit for the design process described in this paper. an experimental flyback converter from the design example has been built and tested to show the validity of the design procedure. table 1. fps lineup for a battery charger figure 1. basic battery charger using fps np n s r sn c sn - v sn + v dc + - ac line d sn d r c o drain vcc gnd fb fps n a d a r a c a h11a817a r d bridge rectifier diode v o l p c p c b c dc i o i o ref v o ref current controller voltage controller v bias h11a817a device switching frequency current limit rdson (typ.) fsdh0165 100 khz 0.35 a 15.6 ? fsd311 67 khz 0.55 a 14 ? fsd200 134 khz 0.32 a 28 ? fsd210 134 khz 0.32 a 28 ?
AN4138 application note 2 ?2002 fairchild semiconductor corporation 2. step-by-step design procedure figure 2. flow chart of design procedure in this section, a design procedure is presented using the schematic of figure 1 as a reference. figure 2 illustrates the design flow chart. the detailed design procedures are as follows: (1) step-1 : define the system specifications - line voltage range ( v line min and v line max ). - line frequency ( f l ). - maximum output power ( p o ). - estimated efficiency ( e ff ) : it is required to estimate the power conversion efficiency to calculate the maximum input power. in the case of a battery charger, the efficiency is relatively low due to the low output voltage and loss in the output current sense resistor. the typical efficiency is about 0.65-0.7. with the estimated efficiency, the maximum input power is given by (2) step-2 : determine dc link capacitor (c dc ) and the dc link voltage range. it is typical to select the dc link capacitor as 2-3uf per watt of input power for universal input range (85-265vrms) and 1uf per watt of input power for european input range (195v- 265vrms). with the dc link capacitor chosen, the minimum link voltage is obtained as where d ch is the dc link capacitor charging duty ratio defined as shown in figure 3, which is typically about 0.2 and p in , v line min and f l are specified in step-1. the maximum dc link voltage is given as where v line max is specified in step-1. figure 3. dc link voltage waveform 1. determine the system specifications (v line min , v line max , f l , po, e ff ) 2. determine dc link capacitor (c dc ) and dc link voltage range 3. determine the reflected output voltage (v ro ) 6. determine the proper core and the minimum primary turns (n p min ) 7. determine the number of turns for each output 8. determine the wire diameter for each winding 9. choose the proper rectifier diode for each output 10. determine the output capacitor 11. design the rcd snubber 12. control circuit design 5. choose proper fps considering input power and i ds peak 4. determine the transformer primary side inductance (l m ) and maximum duty (d max ) is the winding window area (aw) enough ? design finished y n is it possible to change the core ? y n p in p o e ff ------ - = (1) v dc min 2 v line min () ? 2 p in 1d ch ? () ? c dc f l ? ------------------------------------ ? = (2) v dc max 2v line max = (3) dc link voltage minimum dc link voltage t 1 t 2 d ch = t 1 / t 2 = 0.2
application note AN4138 3 ?2002 fairchild semiconductor corporation (3) step-3 : determine the reflected output voltage (v ro ). when the mosfet in the fps is turned off, the input voltage ( v dc ) together with the output voltage reflected to the primary ( v ro ) are imposed on the mosfet as shown in figure 4. after determining v ro, the maximum nominal mosfet voltage ( v ds nom ) is obtained as where v dc max is specified in equation (3). the typical value for v ro is 65-85v. figure 4. the output voltage reflected to the primary (4) step-4 : determine the transformer primary side inductance (l m ) and the maximum duty ratio (d max ). a flyback converter has two kinds of operation modes; continuous conduction mode (ccm) and discontinuous conduction mode (dcm). the operation changes between ccm and dcm as the load condition and input voltage vary and each operation mode has their own advantages and disadvantages, respectively. the transformer size can be reduced using dcm because the average energy stored is lower compared to ccm. however, dcm inherently causes higher rms current, which increases the conduction loss of the mosfet and the current stress on the output capacitors. for low power applications under 10w where the mosfet conduction loss is not so severe, it is typical to design the converter to operate in dcm for the entire operating range, or to operate in ccm only for low input voltage conditions in order to minimize the transformer size. figure 5. simplified flyback converter the design procedures for ccm and dcm are slightly different. once the reflected output voltage (v ro ) is determined in step-3, the flyback converter can be simplified as shown in figure 5 by neglecting the voltage drops in mosfet and diode. for ccm operation, the maximum duty ratio is given by where v dc min and v ro are specified in equations (2) and step-3, respectively. for dcm operation, the maximum duty ratio should be determined as smaller than the value obtained in equation (5). by reducing d max , the transformer size can be reduced. however, this increases the rms value of the mosfet drain current and d max should be determined by trade-off between the transformer size and mosfet conduction loss. with the maximum duty ratio, the primary side inductance ( l m ) of the transformer is obtained. the worst case in designing l m is full load and minimum input voltage v ds nom v dc max v ro + = (4) - v ro + v dc + - drain gnd fps + v ds - 0 v v dc v ro l m v dc min v ro i ds i d i m i m i m i ds i ds d max d max i d i d min dc ro ro v v v + = min dc ro ro v v v + d max v ro v ro v dc min + ------------------------------------- = (5)
AN4138 application note 4 ?2002 fairchild semiconductor corporation condition. therefore, l m is obtained in this condition as where v dc min is specified in equation (2), d max is specified in equation (5), p in is specified in step-1 , f s is the switching frequency of the fps device and k rf is the ripple factor in full load and minimum input voltage condition, defined as shown in figure 6. for dcm operation, k rf = 1 and for ccm operation k rf < 1. the ripple factor is closely related to the transformer size and the rms value of the mosfet current. in the case of low power applications such as battery chargers, a relatively large ripple factor is used in order to minimize the transformer size. it is typical to set k rf = 0.5- 0.7 for the universal input range and k rf = 1.0 for the european input range. once l m is determined, the maximum peak current and rms current of the mosfet in normal operation are obtained as where p in , v dc min , d max and l m are specified in equations (1), (2), (5) and (6) respectively and f s is the fps switching frequency. figure 6. mosfet drain current and ripple factor (k rf ) (5) step-5 : choose the proper fps considering input power and peak drain current. with the resulting maximum peak drain current of the mosfet ( i ds peak ) from equation (7), choose the proper fps of which the pulse-by-pulse current limit level ( i over ) is higher than i ds peak . since fps has 12% tolerance of i over , there should be some margin in choosing the proper fps device. (6) step-6 : determine the proper core and the minimum primary turns. table 2 shows the commonly used cores for battery chargers with output power under 10w. the cores recommended in table 2 are typical for the universal input range and 100khz switching frequency. with the chosen core, the minimum number of turns for the transformer primary side to avoid the core saturation is given by where l m is specified in equation (6), i over is the fps pulse- by-pulse current limit level, a e is the cross-sectional area of the core as shown in figure 7 and b sat is the saturation flux density in tesla. figure 8 shows the typical characteristics of ferrite core from tdk (pc40). since the saturation flux density ( b sat ) decreases as the temperature goes high, the high temperature characteristics should be considered. if there is no reference data, use b sat =0.3~0.35 t. since the mosfet drain current exceeds i ds peak and reaches i over in a transition or fault condition, i over is used in equation (11) instead of i ds peak to prevent core saturation during transition. figure 7. window area and cross sectional area l m v dc min d max ? () 2 2p in f s k rf --------------------------------------------- - = (6) i ds peak i edc ? i 2 ----- + = (7) i ds rms 3i edc () 2 ? i 2 ----- ?? ?? 2 + d max 3 ------------- - =8 () i edc p in v dc min d max ? ------------------------------------- - = (9) ? i v dc min d max l m f s ----------------------------------- = (10) i ? edc i edc rf i i k 2 ? = ccm operation : k rf < 1 i ? edc i edc rf i i k 2 ? = dcm operation : k rf =1 peak ds i peak ds i n p min l m i over b sat a e ------------------- 10 6 (turns) = (11) aw aw aw aw ae ae ae ae
application note AN4138 5 ?2002 fairchild semiconductor corporation figure 8. typical b-h characteristics of ferrite core (tdk/pc40) table 2. typical cores for battery charger (for universal input range, 5v output and fs=100khz) (7) step-7 : determine the number of turns for each output figure 9 shows the simplified diagram of the transformer. first, determine the turns ratio (n) between the primary side and the secondary side. where n p and n s are the number of turns for primary side and reference output, respectively, v o is the output voltage, v f is the diode ( d r ) forward voltage drop and v sense is the maximum voltage drop in the output current sensing resistor. then, determine the proper integer for n s so that the resulting np is larger than n p min obtained from equation (11). the number of turns for vcc winding is determined as where v cc * is the nominal value of the supply voltage of the fps device, and v fa is the forward voltage drop of d a as defined in figure 9. since v cc increases as the output load increases, it is proper to set v cc * as v cc start voltage (refer to the data sheet) to avoid triggering the over voltage protection during normal operation. figure 9. simplified diagram of the transformer with the determined turns of the primary side, the gap length of the core is obtained as where a l is the al-value with no gap in nh/turns 2 , ae is the cross sectional area of the core as shown in figure 8, l m is specified in equation (6) and n p is the number of turns for the primary side of the transformer (8) step-8 : determine the wire diameter for each winding based on the rms current of each output. the rms current of the n-th secondary winding is obtained as where v ro and i ds rms are specified in step-3 and equations (8), v o is the output voltage, v f is the diode ( d r) ) forward voltage drop and d max is specified in equation (5). the current density is typically 5a/mm 2 when the wire is core cross sectional area window area output power range ee13-z 17.1 mm 2 33.4 mm 2 3-5w ei16-z 19.8 mm 2 38.8 mm 2 3-5w ee16-z 21.7 mm 2 51.3 mm 2 5-10w ei19-z 24.0 mm 2 54.4 mm 2 5-10w 100 500 400 300 200 800 1600 0 0 magnetic field h (a/m) flux density b (mt) magnetization curves (typical) material :pc40 100 120 60 25 n n p n s ------- v r0 v o v f v sense ++ -------------------------------------------- - = = (12) n a v cc *v fa + v o v f + ---------------------------- =n s1 ? turns () 13 () np n s - v ro + d r n a d a + v o - + v f - - v fa + + v cc * - - v sense + ) ( sense f o s p ro v v v n n v + + = g40 a e n p 2 1000l m -------------------- - 1 a l ------ ? ?? ?? ?? =mm () 14 () i s rms i ds rms 1d max ? d max ---------------------- - v ro v o v f + () ------------------------ - ? =15 ()
AN4138 application note 6 ?2002 fairchild semiconductor corporation long (>1m). when the wire is short with a small number of turns, a current density of 6-10 a/mm 2 is also acceptable. avoid using wire with a diameter larger than 1 mm to avoid severe eddy current losses as well as to make winding easier. for high current output, it is better to use parallel windings with multiple strands of thinner wire to minimize skin effect. check if the winding window area of the core, a w (refer to figure 8) is enough to accommodate the wires. because bobbin, insulation tape and gaps between wires, the wire can not fill the entire winding window area. typically the fill factor is about 0.15-0.2 for a battery charger. when additional dummy windings are employed for emi shielding, the fill factor is reduced. the required winding window area ( a wr ) is given by where a c is the actual conductor area and k f is the fill factor. if the required window ( a wr ) is larger than the actual window area ( a w ), go back to the step-6 and change the core to a bigger one. sometimes it is impossible to change the core due to cost or size constraints. if so, go back to step-4 and reduce l m by increasing the ripple factor ( k rf ) or reducing the maximum duty ratio. then, the minimum number of turns for the primary ( n p min ) of the equation (11) will decrease, which results in the reduced required winding window area ( a wr ). (9) step-9 : choose the rectifier diode in the secondary side based on the voltage and current ratings. the maximum reverse voltage and the rms current of the output rectifier diode ( d r ) are obtained as where v dc max , d max and i ds rms are specified in equations (3), (5) and (8), respectively, v o is the output voltage, v f is the diode ( d r ) forward voltage and v sense is the maximum voltage drop in the output current sensing resistor. the typical voltage and current margins for the rectifier diode are as follows where v rrm is the maximum reverse voltage and i f is the average forward current of the diode. a quick selection guide for fairchild semiconductor rectifier diodes is given in table 3. table 3. fairchild diode quick selection table (10) step-10 : determine the output capacitor considering the voltage and current ripple. the ripple current of the output capacitor ( c o ) is obtained as where i o is the load current and i d rms is specified in equation (18). the ripple current should be smaller than the ripple current specification of the capacitor. the voltage ripple on the n-th output is given by where c o is the output capacitance, r c is the effective series resistance (esr) of the output capacitor, d max and i ds peak are specified in equations (5) and (7), respectively, i o and v o are the load current and output voltage, respectively, v f is the diode ( d r ) forward voltage and v sense is the maximum voltage drop in the output current sensing resistor. sometimes it is impossible to meet the ripple specification with a single output capacitor due to the high esr of the electrolytic capacitor. then, additional lc filter stages (post filter) can be used. when using the post filters, be careful not to place the corner frequency too low. too low a corner frequency may make the system unstable or limit the control bandwidth. it is typical to set the corner frequency of the post filter at around 1/10~1/5 of the switching frequency. (11) step-11 : design the rcd snubber. when the power mosfet is turned off, there is a high voltage spike on the drain due to the transformer leakage inductance. this excessive voltage on the mosfet may lead to an avalanche breakdown and eventually failure of the fps. therefore, it is necessary to use an additional network to clamp the voltage. the rcd snubber circuit and mosfet drain voltage waveform are shown in figure 10 and 11, respectively. the rcd snubber network absorbs the current in the leakage inductance by turning on the snubber diode ( d sn ) once the mosfet drain voltage exceeds the voltage of node x as depicted in figure 10. in the analysis of snubber network, it is assumed that the snubber capacitor is large enough that its voltage does not change significantly during one switching a w r a c k f ? = (16) v d v o v dc max v o v f v sense ++ () ? v ro --------------------------------------------------------------------------- + =17 () i d rms i ds rms v dc min v ro ------------------- v ro v o v f v sense ++ () ------------------------------------------------- ? =18 () v rrm 1.3 v d ? > (19) i f 1.5 i d rms ? > (20) schottky barrier diode products v rrm i f package sb340 40 v 3 a to-210ad sb350 50 v 3 a to-210ad sb360 60 v 3 a to-210ad i cap rms i d rms () 2 i o 2 ? = (21) ? v o i o d max c o f s ------------------ i ds peak v ro r c v o v f v sense ++ () ------------------------------------------------- ( 2 2 ) + =
application note AN4138 7 ?2002 fairchild semiconductor corporation cycle. the snubber capacitor used should be ceramic or a material that offers low esr. electrolytic or tantalum capacitors are unacceptable due to these reasons. figure 10. circuit diagram of the snubber network the first step in designing the snubber circuit is to determine the snubber capacitor voltage at the minimum input voltage and full load condition ( v sn ). once v sn is determined, the power dissipated in the snubber network at the minimum input voltage and full load condition is obtained as where i ds peak is specified in equation (8), f s is the fps switching frequency, l lk is the leakage inductance, v sn is the snubber capacitor voltage at the minimum input voltage and full load condition, v ro is the reflected output voltage and r sn is the snubber resistor. v sn should be larger than v ro and it is typical to set v sn to be 2~2.5 times v ro . too small a v sn results in a severe loss in the snubber network as shown in equation (23). the leakage inductance is measured at the switching frequency on the primary winding with all other windings shorted. then, the snubber resistor with proper rated wattage should be chosen based on the power loss. the maximum ripple of the snubber capacitor voltage is obtained as where f s is the fps switching frequency. in general, 5~10% ripple of the selected capacitor voltage is reasonable. the snubber capacitor voltage ( v sn ) of equation (26) is for the minimum input voltage and full load condition. when the converter is designed to operate in ccm under this condition, the peak drain current together with the snubber capacitor voltage decrease as the input voltage increases as shown in figure 11. the peak drain current at the maximum input voltage and full load condition ( i ds2 peak ) is obtained as where p in , and l m are specified in equations (1) and (6), respectively and f s is the fps switching frequency. the snubber capacitor voltage under maximum input voltage and full load condition is obtained as where f s is the fps switching frequency, l lk is the primary side leakage inductance, v ro is the reflected output voltage and r sn is the snubber resistor. figure 11. mosfet drain voltage and snubber capacitor voltage from equation (26), the maximum voltage stress on the internal mosfet is given by where v dc max is specified in equation (3). check if v ds max is below 85% of the rated voltage of the mosfet ( bvdss ) as shown in figure 12. the voltage rating of the snubber diode should be higher than bvdss . usually, an ultra fast diode with 1a current rating is used for the snubber network. np r sn c sn - v sn + v dc + - d sn drain gnd fps c dc - v ro + + v ds - l lk v x x p sn v sn () 2 r sn ---------------- - 1 2 -- -f s l lk i ds peak () 2 v sn v sn v ro ? -------------------------- - = = (23) ? v sn v sn c sn r sn f s ------------------------ = (24) i ds2 peak 2p in ? f s l m ? --------------- - = (25) v sn2 v ro v ro () 2 2r sn l lk f s i ds2 peak () 2 + + 2 ------------------------------------------------------------------------------------------------------ - = (26) v dc min v ro v sn v dc max v ro v sn2 i ds peak i ds2 peak minimum input voltage & full load maximum input voltage & full load i ds2 peak < i ds peak ==> v sn2 < v sn v ds max v dc max v sn2 + = (27)
AN4138 application note 8 ?2003 fairchild semiconductor corporation in the snubber design in this section, neither the lossy discharge of the inductor nor stray capacitance is considered. in the actual converter, the loss in the snubber network is less than the designed value due to this effects. figure 12. mosfet drain voltage and snubber capacitor voltage (12) step-12 : design the control circuit. in general, a battery charger employs constant current (cc) / constant voltage (cv) control circuit for an optimal charge of a battery. this design note presents two basic cc/cv control circuits for fps flyback converters. a simple, low cost circuit using a transistor and shunt regulator (ka431) is presented first. the second circuit features highly accurate current control using an op amp together with a shunt regulator (ka431) and secondary bias winding. in the circuit analysis, it is assumed that the ctr of the opto-coupler is 100%. (a) transistor and regulator (ka431) scheme figure 13 shows the cc/cv control circuit using a transistor and ka431 for 5.2v/0.65a output application. this circuit is widely used when low cost and simplicity are major concerns. since the transistor base-emitter voltage drop depends on the temperature, a temperature compensation circuit is required for temperature stability. to turn on the transistor (q), about 0.7v voltage drop across the sensing resistor (r sense ) is required and this current control circuit should be used for output currents below 1a due to the power dissipated in current sense resistor. for output currents greater than 1a, or if output current accuracy and temperature stability are a key factor, the op amp current control circuits shown in figure 15 should be used. figure 13. transistor and ka431 cc/cv control constant voltage (cv) control : the voltage divider network of r 1 and r 2 should be designed to provide 2.5v to the reference pin of the ka431. the relationship between r 1 and r 2 is given by where v o is the output voltage. by choosing r1 to be 2.2k ? , r2 is obtained as the feedback capacitor (c f ) introduces an integrator for cv control. to guarantee stable operation, c f of 470nf is chosen. the resistors r bias and r d should be designed to provide proper operating current for the ka431 and to guarantee the full swing of the feedback voltage for the fps device chosen. in general, the minimum cathode voltage and current for the ka431 are 2.5v and 1ma, respectively. therefore, r bias and r d should be designed to satisfy the following conditions. 0 v v dc max v ro v sn2 effect of stray inductance (5-10v) bvdss voltage margin > 10% of bvdss n s d r c o ka431 817a r d r bias r 1 r 2 c f v o l p c p r sense r base q r th c b v fb 1:1 fps r b gnd i fb i o 250ua 510 56 470nf ksp2222 10k 510 1 5.2v / 0.65a 2.2k 2k r 2 2.5 r 1 ? v o 2.5 ? -------------------- - = (28) r 2 2.5 2.2k ? ? 5.2v 2.5v ? ------------------------------ - 2k ? == v o v op ? 2.5 ? r d -------------------------------------- i fb > (29) v op r bias ------------- -1ma > (30)
application note AN4138 9 ?2003 fairchild semiconductor corporation where v o is the output voltage, v op is opto-diode forward voltage drop, which is typically 1v and i fb is the feedback current of fps. with i fb =0.25ma (fsd210), r d and r bias are determined as 56 ? and 510 ?, respectively. constant current (cc) control : the current control circuit is shown in detail in figure 14. the cc control is implemented using a transistor. because the transistor base- emitter voltage drop varies with the temperature, negative thermal coefficient (ntc) thermistor is used for a temperature compensation. figure 14. current control circuit in detail when the voltage across the sensing resistor is sufficient to turn on the transistor, cc controller is enabled while cv controller is disabled. then, the ka431 consumes very small current and most of the currents through r d and r bias flow into the collector of the transistor q. by assuming that the feedback voltage of fps ( v fb ) is in the middle of its operating range, half of the fps feedback current ( i fb ) sinks into the opto-coupler transistor. since it is also assumed that the ctr of the opto-coupler is 100%, the transistor collector current is given by where i fb is the feedback current of fps, v op is opto-diode forward voltage drop, which is typically 1v. from the circuit in figure 14, i c is obtained as by assuming that the current gain ( ) of q is 100, the transistor base current is obtained as the voltage drop in the sensing resistor ( v sense ) should be set to be 40-100mv higher than the transistor base-emitter voltage ( v be ) at room temperature (25 c). the actual transistor base-emitter voltage (v be ) temperature is measured at room temperature as 0.608v with i c of 2.1ma and v sense is determined to be 0.650v. with the v sense chosen, the sensing resistor ( r sense ) is obtained as where i o is smps output current. it is typical to design the ntc thermistor so that the current through the thermistor would be about 3-6 times of the transistor base current at room temperature. the resistance of the thermistor at room temperature (r th ) is determined as 10 k ? . the current through the thermistor is obtained as the base resistor is determined by variations in the junction temperature of q will cause variations in the value of controlled output current (i o ). the base-emitter voltage decreases with increasing temperature at a rate of approximately 2mv/ c. when the base-emitter voltage is changed to v be t as the temperature changes to t c , the thermistor resistance at t c required to compensate this variation is given by with -2mv/ c, v be reduces to 0.508v from 0.608v as temperature increases from 25 c to 75 c. from equation ka431 r d r bias r sense r base q r th i o = 0.65a 510 56 ksp2222 10k 510 1 i rth b e c i fb /2 + v op - i c i b v be v sense i c i fb r d ? () 2 ? v op + r bias ------------------------------------------------ 1 2 -- - i fb ? + = (31) i c 250 a56 ? ? () 2 ? 1v + 510 ? ------------------------------------------------------------ - 1 2 -- - 250 a ? + 2.1ma == i b i c ---- - 2.1ma 100 ----------------- - 21ua = = = (32) r sense v sense i o ----------------- - 0.65v 0.65a --------------- -1 ? = = = (33) i rth v be r th ---------- - 0.608v 10k ? ------------------ -61 a = = = (34) r base v sense v be ? v be r th ---------- -i b + ---------------------------------- 0.65v 0.608v ? 0.608v 10k ? ------------------ -21 a + ---------------------------------------- - 513 ? = = = (35) r th t v be t v sense v be t ? r base ------------------------------------- -i b ? ------------------------------------------------ - = (36)
AN4138 application note 10 ?2003 fairchild semiconductor corporation (36), the resistance of the thermistor at 75 c to keep the same output current is given by ntc thermistor 103 2 from dsc is chosen for the compen- sation, whose resistance is 10k ? at 25 c and 1.92k ? at 75 c. (b) op amp and shunt regulator (ka431) scheme figure 15 shows a 4.2 v, 0.8a cc/cv control circuit using the lm358 dual op amp shunt regulator (ka431). this circuit provides higher accuracy compared with the simple transistor circuit. power loss is lower and efficiency is better because smaller resistance values can be used for sense resistor r sense . the shunt regulator (ka431) is used as a voltage reference for an accurate control. constant voltage (cv) control : the output voltage is sensed by r1 and r2 and then compared by op amp lm358b to reference of 2.5v. the output of the op amp drives current through d 2 and r d into the led of the opto- coupler. the voltage divider network of r 1 and r 2 should be designed to provide 2.5v to the reference pin of the ka431. the relationship between r 1 and r 2 is given by where v o is the output voltage. by choosing r 1 to be 680 ? , r 2 is obtained as c f2 , r f2 , and r 6 compensate the voltage control loop. constant current (cc) control : the voltage drop across the sensing resistor (r sense ) is given by it is typical to set v sense as 0.1-0.2v. since the inverting input of op amp is virtually grounded, the relationship between r4 and r5 is given by by choosing r5 as 33k ?, r4 is obtained as 2.1k ?. c f2 , r f2 , and r 6 compensate the current control loop. 0.508v 0.65v 0.508v ? 513 ---------------------------------------- -21 a ? -------------------------------------------------------------- 1 . 9 9 k = r 2 2.5 r 1 ? v o 2.5 ? -------------------- - = (37) r 2 2.5 680 ? 4.2 v2.5v ? ------------------------------- 1k ? == v sense i o r sense =38 () r 4 v sense r 5 ? 2.5 ----------------------------- = (39)
application note AN4138 11 ?2003 fairchild semiconductor corporation figure 15. cc/cv control using op amp and shunt regulator n s d r c o h11a817a r d r 1 r 2 v o l p c p r sense d bias c bias v bias r 3 ka431 v ref =2.5v r 4 r 5 c f1 c f2 lm358a lm358b 1 3 2 4 8 5 6 7 i o n bias c b v fb 1:1 fps r b gnd i fb 1n4148 r f1 0.2 4.2v 0.8a 680 1.0k 4.7k r f2 4.7k 0.1uf 1k r 6 100k 200 0.1uf 33k 2.1k 1n4148 d 1 d 2
AN4138 application note 12 ?2002 fairchild semiconductor corporation - summary of symbols - a w : winding window area of the core in mm 2 ae : cross sectional area of the core in mm 2 b sat : saturation flux density in tesla. c o : output capacitor d max : maximum duty cycle ratio e ff : estimated efficiency f l : line frequency f s : switching frequency of fps i ds peak : maximum value of peak current through mosfet at the minimum input voltage condition i ds2 peak : maximum value of peak current through mosfet at the maximum input voltage condition i ds rms : rms current of mosfet i ds2 : maximum peak drain current at the maximum input voltage condition. i over : fps current limit level. i se rms : rms current of the secondary winding i d rms : maximum rms current of the output rectifier diode i cap rms : rms ripple current of the output capacitor i o : output load current k rf : current ripple factor l m : transformer primary side inductance l lk : transformer primary side leakage inductance loss sn : maximum power loss of the snubber network in normal operation n p min : the minimum number of turns for the transformer primary side to avoid saturation n p : number of turns for primary side winding n s : number of turns for the output winding n a : number of turns for the vcc winding p o : maximum output power p in : maximum input power r c : effective series resistance (esr) of the output capacitor. r sn : snubber resistor r l : effective total output load resistor of the controlled output v line min : minimum line voltage v line max : maximum line voltage v dc min : minimum dc link voltage v dc max : maximum dc line voltage v ds nom : maximum nominal mosfet voltage v o : output voltage v f : forward voltage drop of the output rectifier diode. v cc * : nominal voltage for vcc v fa : diode forward voltage drop of vcc winding v d : maximum voltage of the output rectifier diode v ro : output voltage reflected to the primary v sn : snubber capacitor voltage under minimum input voltage and full load condition v sn2 : snubber capacitor voltage under maximum input voltage and full load condition v ds max : maximum voltage stress of the mosfet
application note AN4138 13 ?2002 fairchild semiconductor corporation ? the estimated efficiency (e ff ) is set to be 0.65, considering the low output voltage and the loss in the current sensing resistor. design example using fps design assistant 5% ripple spec 5.2v (0.65a) 85v-265vac 3.4w fsd210 battery charger output voltage (max current) input voltage output power device application 5% ripple spec 5.2v (0.65a) 85v-265vac 3.4w fsd210 battery charger output voltage (max current) input voltage output power device application ? since the input power is 5.2 w, the dc link capacitor is set to be 9.4uf by 2uf/watt. (4.7uf 2) ? v ro is set to be 70v so that v ds nom would be about 70% of 650v. 1 . d e fin e th e syst e m sp e cifications 1 . d e fin e th e syst e m sp e cifications 1 . d e fin e th e syst e m sp e cifications 1 . d e fin e th e syst e m sp e cifications minimum lin e voltag e (v lin e min )85v.rms maximum lin e voltag e (v lin e max )265v.rms lin e fr e qu e ncy (f l )60hz v v v v o(n) o(n) o(n) o(n) i ii i o(n) o(n) o(n) o(n) p p p p o(n) o(n) o(n) o(n) output 5.2 v 0.65 a 3 3 3 3 w w w w maximum output po we r (p maximum output po we r (p maximum output po we r (p maximum output po we r (p o o o o ) = ) = ) = ) =3.4 3.4 3.4 3.4 w w w w estimat e d e ffici e ncy (e ff )65% maximum input po we r (p maximum input po we r (p maximum input po we r (p maximum input po we r (p in in in in ) = ) = ) = ) =5.2 5.2 5.2 5.2 w w w w 2. d e t e rmin e dc link capacitor and dc link voltag e rang e 2. d e t e rmin e dc link capacitor and dc link voltag e rang e 2. d e t e rmin e dc link capacitor and dc link voltag e rang e 2. d e t e rmin e dc link capacitor and dc link voltag e rang e dc link capacitor (c dc )9.4uf minimum dc link voltag e (v minimum dc link voltag e (v minimum dc link voltag e (v minimum dc link voltag e (v dc dc dc dc min min min min ) = ) = ) = ) =84 84 84 84 v v v v maximum dc link voltag e (v maximum dc link voltag e (v maximum dc link voltag e (v maximum dc link voltag e (v dc dc dc dc max max max max )= )= )= )= 375 375 375 375 v v v v 3. d e t e rmin e maximum duty ratio (dmax) 3. d e t e rmin e maximum duty ratio (dmax) 3. d e t e rmin e maximum duty ratio (dmax) 3. d e t e rmin e maximum duty ratio (dmax) output voltag e r e fl e ct e d to primary (v ro )= 70 v maximum duty ratio (d max ) 0.456 0.456 0.456 0.456 max nominal mosfet voltag e (v max nominal mosfet voltag e (v max nominal mosfet voltag e (v max nominal mosfet voltag e (v ds ds ds ds nom nom nom nom ) = ) = ) = ) =445 445 445 445 v v v v 4. d e t e rmin e transform e r primary inductanc e (lm) 4. d e t e rmin e transform e r primary inductanc e (lm) 4. d e t e rmin e transform e r primary inductanc e (lm) 4. d e t e rmin e transform e r primary inductanc e (lm) s w itching fr e qu e ncy of fps (f s ) 1 34 khz rippl e factor (k rf )0.66 primary sid e inductanc e (l primary sid e inductanc e (l primary sid e inductanc e (l primary sid e inductanc e (l m m m m ) = ) = ) = ) = 1 597 1 597 1 597 1 597 uh uh uh uh maximum p e ak drain curr e nt (i maximum p e ak drain curr e nt (i maximum p e ak drain curr e nt (i maximum p e ak drain curr e nt (i ds ds ds ds p e ak p e ak p e ak p e ak ) = ) = ) = ) =0.23 0.23 0.23 0.23 a a a a rms drain curr e nt (i rms drain curr e nt (i rms drain curr e nt (i rms drain curr e nt (i ds ds ds ds rms rms rms rms ) = ) = ) = ) =0. 1 0 0. 1 0 0. 1 0 0. 1 0 a a a a 63 maximum dc link voltag e in ccm (v maximum dc link voltag e in ccm (v maximum dc link voltag e in ccm (v maximum dc link voltag e in ccm (v dc dc dc dc ccm ccm ccm ccm ) ) ) ) 1 43 1 43 1 43 1 43 v v v v i ? edc i edc rf i i k 2 ? = ) ( 1 ) ( 1 ccm k dcm k rf rf < =
AN4138 application note 14 ?2002 fairchild semiconductor corporation ? ferrite core ee1616 is chosen (ae=19.4 mm 2 ) ? the voltage drop in the sensing resistor (0.7v) is included in the diode voltage drop of the output diode. (0.7v + 0.5v = 1.2v) ? since the winding for 5.2v is short with small number of turns, relatively large current density (> 5a/mm 2 ) is allowed. 7. d e t e rmin e th e numb e r of turns for e ach output 7. d e t e rmin e th e numb e r of turns for e ach output 7. d e t e rmin e th e numb e r of turns for e ach output 7. d e t e rmin e th e numb e r of turns for e ach output v v v v o(n) o(n) o(n) o(n) v v v v f(n) f(n) f(n) f(n) # of turns # of turns # of turns # of turns vcc (us e vcc start voltag e ) vcc (us e vcc start voltag e ) vcc (us e vcc start voltag e ) vcc (us e vcc start voltag e ) 1 2v 0.8v 1 8.0 1 8.0 1 8.0 1 8.0 => 1 8 1 8 1 8 1 8 t t t t 1 st output for f ee dback 1 st output for f ee dback 1 st output for f ee dback 1 st output for f ee dback 5.2 5.2 5.2 5.2 v v v v 1 .2 v 9 => 9 9 9 9 t t t t vf : for w ard voltag e drop of r e ctifi e r diod e primary turns (n primary turns (n primary turns (n primary turns (n p p p p )= )= )= )= 99 99 99 99 t t t t ---> e nough turns ---> e nough turns ---> e nough turns ---> e nough turns ungapp e d a l valu e ( a l) 11 50 nh/t 2 gap l e ngth (g) ; c e nt e r pol e gap = gap l e ngth (g) ; c e nt e r pol e gap = gap l e ngth (g) ; c e nt e r pol e gap = gap l e ngth (g) ; c e nt e r pol e gap =0. 1 3 0. 1 3 0. 1 3 0. 1 3 mm mm mm mm schottky barrier diode sb260 (60v/2a, vf=0.55v) output (5.2v) ultra fast recovery diode uf4003 (200v /1a, vf=1v) vcc winding schottky barrier diode sb260 (60v/2a, vf=0.55v) output (5.2v) ultra fast recovery diode uf4003 (200v /1a, vf=1v) vcc winding 5. choos e th e prop e r fps consid e ring th e input po we r and curr e nt limit 5. choos e th e prop e r fps consid e ring th e input po we r and curr e nt limit 5. choos e th e prop e r fps consid e ring th e input po we r and curr e nt limit 5. choos e th e prop e r fps consid e ring th e input po we r and curr e nt limit typical curr e nt limit of fps (i ov e r )0.32 a minimum i minimum i minimum i minimum i ov e r ov e r ov e r ov e r consid e ring tol e ranc e of 1 2% consid e ring tol e ranc e of 1 2% consid e ring tol e ranc e of 1 2% consid e ring tol e ranc e of 1 2% 0.28 0.28 0.28 0.28 a a a a > > > > a a a a ->o.k. ->o.k. ->o.k. ->o.k. 6. d e t e rmin e th e prop e r cor e and th e minimum primary turns 6. d e t e rmin e th e prop e r cor e and th e minimum primary turns 6. d e t e rmin e th e prop e r cor e and th e minimum primary turns 6. d e t e rmin e th e prop e r cor e and th e minimum primary turns saturation flux d e nsity (b sat )0.30t cross s e ctional ar e a of cor e ( a e ) 1 9.4 mm 2 minimum primary turns (n minimum primary turns (n minimum primary turns (n minimum primary turns (n p p p p min min min min )= )= )= )= 87.8 87.8 87.8 87.8 t t t t 0.23 0.23 0.23 0.23 8. d e t e rmin e th e w ir e diam e t e r for e ach w inding 8. d e t e rmin e th e w ir e diam e t e r for e ach w inding 8. d e t e rmin e th e w ir e diam e t e r for e ach w inding 8. d e t e rmin e th e w ir e diam e t e r for e ach w inding diam e t e r diam e t e r diam e t e r diam e t e r parall e l parall e l parall e l parall e l i ii i d(n) d(n) d(n) d(n) rms rms rms rms ( a /mm ( a /mm ( a /mm ( a /mm 2 2 2 2 ) ) ) ) primary w inding primary w inding primary w inding primary w inding 0. 1 6m m 1 t 0. 1 0. 1 0. 1 0. 1 a a a a 4.9 4.9 4.9 4.9 vcc w inding vcc w inding vcc w inding vcc w inding 0. 1 6m m 2 t 0. 1 0. 1 0. 1 0. 1 a a a a 2.5 2.5 2.5 2.5 output w inding output w inding output w inding output w inding 0.4 m m 1 t 1 .2 1 .2 1 .2 1 .2 a a a a 9.4 9.4 9.4 9.4 copp e r ar e a ( a copp e r ar e a ( a copp e r ar e a ( a copp e r ar e a ( a c c c c ) = ) = ) = ) =3.84 3.84 3.84 3.84 mm mm mm mm 2 2 2 2 fill factor (k f )0. 1 5 r e quir e d w indo w ar e a ( a r e quir e d w indo w ar e a ( a r e quir e d w indo w ar e a ( a r e quir e d w indo w ar e a ( a w r w r w r w r ) ) ) ) 25.62 25.62 25.62 25.62 mm mm mm mm 2 2 2 2 9. choos e th e r e ctifi e r diod e in th e s e condary sid e 9. choos e th e r e ctifi e r diod e in th e s e condary sid e 9. choos e th e r e ctifi e r diod e in th e s e condary sid e 9. choos e th e r e ctifi e r diod e in th e s e condary sid e v v v v d(n) d(n) d(n) d(n) i ii i d(n) d(n) d(n) d(n) rms rms rms rms vcc diod e vcc diod e vcc diod e vcc diod e 80 80 80 80 v v v v0. 1 0 0. 1 0 0. 1 0 0. 1 0 a a a a 1 st output diod e 1 st output diod e 1 st output diod e 1 st output diod e 39 39 39 39 v v v v 1 . 1 8 1 . 1 8 1 . 1 8 1 . 1 8 a a a a
application note AN4138 15 ?2002 fairchild semiconductor corporation since the output voltage ripple exceeds the ripple spec of 5%, additional lc filter stage should be used. 330uf capacitor together with 3.9uh inductor are used for the post filter. ? the snubber capacitor and snubber resistor are chosen as 1nf and 94k (47k ? 2), respectively. the maximum voltage stress on the mosfet is below 80% of bvdss (700v) 1 0. d e t e rmin e th e output capacitor 1 0. d e t e rmin e th e output capacitor 1 0. d e t e rmin e th e output capacitor 1 0. d e t e rmin e th e output capacitor 1 st output capacitor 1 st output capacitor 1 st output capacitor 1 st output capacitor 330 uf 200 m ? 1 .0 1 .0 1 .0 1 .0 a a a a 0.50 0.50 0.50 0.50 v v v v v v v v o(n) o(n) o(n) o(n) c c c c o(n) o(n) o(n) o(n) r r r r c(n) c(n) c(n) c(n) i ii i cap(n) cap(n) cap(n) cap(n) 11 . d e sign rcd snubb e r 11 . d e sign rcd snubb e r 11 . d e sign rcd snubb e r 11 . d e sign rcd snubb e r primary sid e l e akag e inductanc e (l lk )50 uh maximum voltag e of snubb e r capacitor (v sn ) 1 70 v maximum snubb e r capacitor voltag e rippl e 9 % snubb e r r e sistor (r snubb e r r e sistor (r snubb e r r e sistor (r snubb e r r e sistor (r sn sn sn sn )= )= )= )= 99.6 99.6 99.6 99.6 ? ? ? ? snubb e r capacitor (c snubb e r capacitor (c snubb e r capacitor (c snubb e r capacitor (c sn sn sn sn )= )= )= )= 0.8 0.8 0.8 0.8 nf nf nf nf 0. 1 58 1 po we r loss in snubb e r r e sistor (p po we r loss in snubb e r r e sistor (p po we r loss in snubb e r r e sistor (p po we r loss in snubb e r r e sistor (p sn sn sn sn )= )= )= )= 0.3 0.3 0.3 0.3 w w w w (in normal op e ration) (in normal op e ration) (in normal op e ration) (in normal op e ration) p e ak drain curr e nt at v p e ak drain curr e nt at v p e ak drain curr e nt at v p e ak drain curr e nt at v dc dc dc dc max max max max (i (i (i (i ds2 ds2 ds2 ds2 ) = ) = ) = ) =0.22 0.22 0.22 0.22 a a a a max voltag e of csn at v max voltag e of csn at v max voltag e of csn at v max voltag e of csn at v dc dc dc dc max max max max (v (v (v (v sn2 sn2 sn2 sn2 )= )= )= )= 1 67 1 67 1 67 1 67 v v v v max voltag e str e ss of mosfet (v max voltag e str e ss of mosfet (v max voltag e str e ss of mosfet (v max voltag e str e ss of mosfet (v ds ds ds ds max max max max )= )= )= )= 542 542 542 542 v v v v
AN4138 application note 16 ?2002 fairchild semiconductor corporation design summary features ? high efficiency (>60% at universal input) ? low power consumption (<100mw at 240vac) with no load ? low component count ? enhanced system reliability through various protection functions ? internal soft-start (3ms) ? frequency modulation for low emi key design notes ? the constant voltage (cv) mode control is implemented with resistors, r8, r9, r10 and r12, shunt regulator, u2, feedback capacitor, c9 and opto-coupler, u3. ? even though fsd210 has an internal soft start, c10 is employed to provide longer soft start time. since c10 reduces the feedback gain, a relatively small resistor is used for r9 in order to compensate it. ? the constant current (cc) mode control is realized with resistors, r8, r9, r15, r16, r17 and r19, npn transistor, q1 and ntc, th1. when the voltage across current sensing resistors, r15,r16 and r17 is 0.7v, the npn transistor turns on and the current through the opto coupler led increases. this reduces the feedback voltage and duty ratio. therefore, the output voltage decreases and the output current is kept constant. ? the ntc (negative thermal coefficient) is used to compensate the temperature characteristics of the transistor q1. figure 16. the final schematic of the flyback converter for fsd2 1 x for fsd2 1 x for fsd2 1 x for fsd2 1 x l3 4uh c8 330uf 16v l1 330uh r19 510r r8 510r d6 1n4148 r3 47k th1 10k vo . r15 3r0 r5 39r q1 ksp2222a 1 u2 tl431 d1 1n4007 r16 3r0 c9 470nf tx1 r10 2.2k c2 4.7uf 400v 0 3 c4 100nf h11a817b u3 r1 4.7k 4 c1 4.7uf 400v c5 33uf 50v 7 fuse 1w, 10r c6 152m-y, 250vac d3 1n4007 8 h11a817b 2 1 r7 4.7m, 1/4w ac r17 3r0 d2 1n4007 d4 1n4007 r9 56r d5 uf4007 ac 0 r12 2k c7 330uf 16v (5.2v/0.65a) r4 47k c10 4.7uf 50v u1 fsd210 8 5 7 1 4 2 3 vstr vcc drain gnd vfb gnd gnd d7 sb260 r6 4.7m 1/4w 0 c3 102k 1kv
application note AN4138 17 ?2002 fairchild semiconductor corporation experimental verification in order to show the validity of the design procedure presented in this paper, the converter of the design example has been built and tested. all the circuit components are used as designed in the design example and the detailed transformer structure is shown in figure 17. the winding specifications and measured transformer characteristics are shown in table 4 and 5, respectively. the dummy winding (w3) is used as an emi shield. this winding improves emi characteristics by screening the radiation noise generated from the primary winding. figure 17. transformer structure table 4. winding specifications table 5. the measured transformer characteristics figure 18 shows the fps drain current and voltage waveforms at the minimum input voltage and full load condition. as designed, the maximum peak drain current ( i ds peak ) is about 0.23a. figure 19 shows the fps drain current and voltage waveforms at the maximum input voltage and full load condition. the maximum voltage stress on the mosfet is about 520v, which is lower than the designed value (542v). this is because of the lossy discharge of the inductor or the stray capacitance. the measured efficiencies at full load for different input voltages are shown in figure 20. the minimum efficiency is 61% at 265v input voltage. the efficiencies are a little bit low due to the power loss in the current sensing resistor in the output. the components for cc/cv control circuit are chosen as designed in design procedure of step-12. figure 21 and 22 show the output voltage vs. output current characteristics at 25 c and 75 c , respectively. as designed, the output voltage is 5.2v and the output current is 0.65a. the output current variation with temperature is very small due to the temperature compensation circuit with thermistor. table 6 shows the power consumption in the standby mode. through the burst mode operation, the power consumption is minimized. the power consumption at 240v input is under 100 mw. the detailed burst operation waveforms are shown in figure 23 and 24. by disabling and enabling the switching operation according to the feedback voltage, the effective switching frequency is reduced, which also reduces the power consumption in the standby mode. figure 18. waveforms of drain current and voltage at 85vac and full load condition 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 8 8 8 8 7 7 7 7 6 6 6 6 5 5 5 5 w4 w3 w2 w1 2mm 2mm insulation : polyester tape t=0.025mm / 10mm, 3ts solenoid winding 9 ts 0.40 ? 1 8 7 w4 insulation : polyester tape t=0.025mm / 10mm, 3ts solenoid winding 50 ts 0.16 ? 1 1 open w3 insulation : polyester tape t=0.025mm / 10mm, 2ts center solenoid winding 18 ts 0.16 ? 1 4 3 w2 insulation : polyester tape t=0.025mm / 10mm, 2ts solenoid winding 99 ts 0.16 ? 1 1 2 w1 winding method winding method turns turns wire wire pin (s pin (s f) f) no. no. insulation : polyester tape t=0.025mm / 10mm, 3ts solenoid winding 9 ts 0.40 ? 1 8 7 w4 insulation : polyester tape t=0.025mm / 10mm, 3ts solenoid winding 50 ts 0.16 ? 1 1 open w3 insulation : polyester tape t=0.025mm / 10mm, 2ts center solenoid winding 18 ts 0.16 ? 1 4 3 w2 insulation : polyester tape t=0.025mm / 10mm, 2ts solenoid winding 99 ts 0.16 ? 1 1 2 w1 winding method winding method turns turns wire wire pin (s pin (s f) f) no. no. core ee1616 (isu ceramics) primary side inductance 1.6 mh @ 100khz leakage inductance 50 uh @100khz with all other windings shorted.
AN4138 application note 18 ?2002 fairchild semiconductor corporation figure 19. waveforms of drain current and voltage at 265vac and full load condition figure 20. measured efficiency at full load for different input voltage figure 21. output voltage (vo) vs. output current (io) characteristics @ 25 c figure 22. output voltage (vo) vs. output current (io) characteristics @ 75 c table 6. standby power consumption figure 23. burst mode waveforms at 85vac and full load condition effici e ncy (%) 60.0% 6 1 .0% 62.0% 63.0% 64.0% 65.0% 85 11 5 1 45 1 75 205 235 265 input voltage input power 85vac 54 mw 240vac 92 mw 265vac 110 mw
application note AN4138 19 ?2002 fairchild semiconductor corporation figure 24. burst mode waveforms at 265vac and full load condition
AN4138 application note 3/24/04 0.0m 002 ? 2003 fairchild semiconductor corporation disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corproation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com by hang-seok choi / ph. d power supply group / fairchild semiconductor phone : +82-32-680-1383 facsimile : +82-32-680-1317 e-mail : hschoi@fairchildsemi.co.kr

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